1. Field of the Invention
The present invention relates to a semiconductor memory device having a function of inhibiting an access to a memory region having a defect.
2. Description of the Related Art
In recent years, along with a development of semiconductor fine processing technologies, a remarkable development has been made to attain a larger capacity of a semiconductor memory. For example, a flash memory for storing files has already reached a capacity of 1G bits and is still under development of a larger capacity. On the other hand, however, a large number of defect points also arise. Particularly when making a memory cell finer, an effect of microscopic unevenness due to the production steps becomes large statistically and an occurrence rate of a cell defect itself becomes high. They appear as a large number of small defects arising on an entire chip.
Generally, a relief of a defect in a semiconductor memory is performed as below.
First, a one-system or two-system redundant word line group or redundant bit line group is prepared for each memory array, and a defect map corresponding to each redundant field is provided. A flag indicating whether a corresponding redundant field is used or not and position information of defect points are programmed in each of the defect maps by normally using a fuse. When an access is made to a memory array, the defect map is referred to, and an existence of a defect and a defect point thereof are specified and replaced by a redundant field.
However, because defects arising randomly in a small unit have increased in recent years as explained above, they cannot be fully handled by the defect relief method of the related art. Namely, in the above mentioned method of the related art, it becomes extremely difficult to relieve when a large number of small defects arise in one cell array. In that case, the entire chip becomes defective even if all other arrays are good. Accordingly, there are demands for a more flexible defect relief method having a high relief efficiency.
On the other hand, a method called remapping is sometimes used as a measure for correcting such defects of a semiconductor memory on the host apparatus side for accessing the semiconductor memory. This is a method of skipping defect points and using only normal parts by providing a second memory for storing an address transformation table on the host apparatus side and performing address transformation.
FIG. 8 is a view of a configuration example of a general system for performing remapping.
A host apparatus 1 is, for example, a computer having a CPU and accesses to a first memory 2 and a second memory 3 via a bus.
The first memory 2 is a block access memory for storing files. A size of one block is, for example, 512 bytes, and an address space is divided in units of blocks each having 512 bytes. When assuming that a memory capacity of the first memory 2 is 1 G bits, the number of blocks is 256 k (The “k” after the number indicates that the number is multiplied with 1024. It will be the same below.). In this case, the number of address bits is 18 bits, and a physical address region indicated by the hexadecimal system is “00000” to “3FFFF”.
Also, the first memory 2 has spare bits for marking parity bits and defects, and a defect can be detected by examining these bits when reading data.
The second memory 3 is a memory provided separately for storing an address transformation table of the first memory 2. The host apparatus 1 accesses to the first memory 2 via the address transformation table of the second memory 3.
Normally, the second memory 3 is a semiconductor memory used as a main memory in the host apparatus 1 and the address transformation table is stored in a part of the region. When the second memory 3 is a DRAM of a 16-bit configuration, a physical address to be a pointer to the first memory 2 is stored in a two-word amount of the memory region.
FIG. 9 is a schematic view of remapping in the system shown in FIG. 8.
The host apparatus 1 scans contents of the first memory 2 successively from the 0 address in the physical address and, when the read portion is good, maps the address in the second memory 3. In the example in FIG. 9, two words are used each time from the physical address “10000” of the second memory 3 to map effective physical addresses of the first memory 2. The physical addresses “00001” and “00004” are defective in the first memory 2 and their physical addresses are deleted from the address transformation table in the second memory 3. In the present embodiment, a total of 15 defective blocks exist and the end of the logical address is “3FFF0”.
When a table as above is once constructed, the host apparatus 1 accesses to the first memory 2 always via the table after that. When an application accesses a file, the logical address shown in FIG. 9 is used directly, and the logical address is transformed to a physical address in the first memory 2 based on the address transformation table in the second memory 3.
For example, when assuming that a logical address A1 is specified by an application, the host apparatus 1 calculates an address A2 in the second memory 2 by A2=10000+2×A1, and reads a two-word amount of data from the address A2. Then, an access to the first memory 2 is made by using the read data as the physical address in the first memory 2.
When the above method is used, even if some defective blocks exist, only good blocks can be used by eliminating them from the address transformation table and a defect relief can be flexibly performed.
[Patent Article 1] The Japanese Unexamined Patent Publication No. 11-120788